TAKE5 is the next in a chain of thematically connected semiconductor “Key Enabling Technology” (KET) ENIAC-JU pilot line projects which deal with with 450mm/300mm development for the 10nm technology node, and the ECSEL JU project SeNaTe, aiming at the 7nm technology node. The main objective is the demonstration of 5nm patterning, in line with industry needs and the “International Technology Roadmap for Semiconductors” (ITRS), in the Advanced Patterning Center at the imec research centre’s pilot line (Belgium). This is to be achieved by using innovative design and technology co-optimization, layout and device architecture exploration, demonstrating a lithographic platform for EUV (“Extreme Ultra-Violet” light) technology, and advanced process and holistic metrology platforms and new materials.
A lithography scanner will be developed, based on EUV technology to achieve the 5nm module patterning specification. Metrology platforms need to be qualified for 5nm patterning of 1D, 2D and 3D geometries with the appropriate precision and accuracy. For the 5nm technology modules, new materials will need to be introduced, bringing challenges for all involved deposition processes and the related equipment set. Next to new deposition processes, the interaction of the involved materials with subsequent steps will be studied. The project will be dedicated to find the best options for patterning.
The project relates to the ECSEL work program topic Process technologies – More Moore. It targets, as set out in the MASP, the discovery of new Semiconductor Process, Equipment and Materials solutions for advanced CMOS processes that enable the nano-structuring of electronic devices with 5nm resolution in high-volume manufacturing and fast prototyping. The project touches the core of the continuation of Moore’s law (which has recently celebrated its 50th anniversary on April 19th 2015) and covers all aspects of 5nm patterning development.